1. Field of the Invention
The present invention relates to: a hardware verification programming description generation apparatus for generating a model as a general programming description that can verify, at a cycle precision level, a process behavior of a circuit of hardware operating in accordance with a multi-phase clock; a high-level synthesis apparatus; a hardware verification programming description generation method using the hardware verification programming description generation apparatus; a hardware verification program generation method using the hardware verification programming description generation method; a hardware verification programming description generation program for causing a computer to execute the procedure of processes of the hardware verification programming description generation method; a control program (e.g., hardware verification program) using the hardware verification programming description generation program; and a computer-readable recording medium having the control program recorded thereon.
2. Description of the Related Art
In a conventional development of system LSI, it is necessary to verify whether a behavior of a circuit of designed hardware satisfies the specification required by a system. Conventionally, a hardware description language (HDL) simulator is used in order to perform a verification at a cycle precision level. The cycle precision level to be described herein refers to a precision level that can show the state of hardware in a clock cycle unit in a behavior of a circuit of the hardware. For example, in hardware operating in synchronization with a rising edge of a clock, the state of a memory device (e.g., register, memory or the like) in the hardware at the rising edge of the clock is shown. In the HDL simulator, a performance (e.g., operation speed or the like) is measured so as to verify whether a required specification is satisfied. Generally, in the HDL simulator, a behavior of a circuit that is described by a hardware description language such as VHDL is simulated. The simulation is performed by an event-driven system by the HDL simulator monitoring the change in a signal in a circuit in a time unit that is shorter than a clock cycle, and the change in the signal in the circuit is transmitted to a signal in a circuit connected to the circuit having the changed signal.
Further, in the conventional development of LSI system, the design of hardware is sometimes performed using a multi-phase clock. In this case, when the hardware is designed, processes having relevancy to each other are gathered and divided into function blocks. In order to satisfy the functional specification required by the hardware, the clock frequency of a function block that has to perform an operation at a high speed is set high such that the clock cycle thereof is short. On the other hand, the clock frequency of a function block that dose not has to perform an operation at a high speed is set low such that the clock cycle thereof is long. As described above, the hardware is designed so as to include function blocks that operate at clock cycles different from each other for one hardware, and the behavior of the circuit of the hardware is verified.
For example, Reference 1 discloses a method in which a verification model is generated by a general programming language and the verification of hardware at a cycle precision level is performed at a high speed, by analyzing a behavioral description of the hardware, generating a control data flow graph (CDFG) based on the behavioral description of the hardware, and creating a behavioral description that shows the behaviors of all the computations based on the information of a behavior of the hardware that are divided into states and data path information. The behavioral description of the hardware only describes a process behavior of the hardware but does not describe information regarding a structure of the hardware. In addition, the CDFG represents nodes, in which operations (e.g., computations or the like) are performed by hardware, and branches connecting between the nodes for a flow of data.
For example, Reference 2 discloses a method for generating a clock precision verification programming description for hardware for the purpose of verifying a process behavior of the hardware at a higher speed than the HDL simulator. This method will be described with reference to FIG. 6.
FIG. 6 is a block diagram showing an exemplary essential structure of a conventional hardware verification programming description generation apparatus.
As shown in FIG. 6, first, a behavior synthesis section 61 generates CDFG data 72 based on a behavioral description 71 of a circuit of hardware operating in accordance with a single-phase clock. Next, the CDFG data 72 is scheduled according to an operating frequency required by a hardware specification and allocated for states. Thereafter, a clock precision model generation section 62 generates behavior models for respective nodes using the operation information of the nodes that is included in the CDFG data 72 and decides the order of the computations of the behavior models for the respective nodes using node connection information. Therefore, the clock precision model generation section 62 generates a model that can be simulated at each state and generates a HW clock precision description 73 that can verify the hardware at a cycle precision level.
For example, Reference 3 discloses a conventional technique of a high-level synthesis method that is also used in the present invention.
[Reference 1] Japanese Laid-Open Publication No. 2001-14356
[Reference 2] Japanese Laid-Open Publication No. 2006-139729
[Reference 3] Japanese Laid-Open Publication No. 5-101141